1. Technology Field
The present invention generally relates to a flash memory control circuit, and more particularly, to a flash memory controller capable of identifying error data in a flash memory, a flash memory storage system, and a method for identifying the error data in the flash memory.
2. Description of Related Art
Along with the widespread of digital cameras, cell phones, and MP3 in recently years, the consumers' demand to storage media has increased drastically. Flash memory is one of the most adaptable memories for such battery-powered portable products due to its characteristics such as data non-volatility, low power consumption, small volume, and non-mechanical structure. A solid state drive (SSD) is a storage device which uses a NAND flash memory as its storage medium.
An error correcting circuit is usually adopted in the design of a flash memory storage device for verifying whether data stored in the flash memory storage device is accurate. To be specific, if a computer host connected with the flash memory storage device transmits data to the flash memory storage device, the error correcting circuit in the flash memory storage device generates an error correcting code corresponding to the data, and a control circuit in the flash memory storage device writes the data and the error correcting code into a flash memory of the flash memory storage device. Subsequently, when the computer host is about to read the data from the flash memory storage device, the control circuit reads the data and the corresponding error correcting code from the flash memory, and the error correcting circuit executes an error correcting process according to the data and the corresponding error correcting code to ensure the accuracy of the data. If the data is accurate, the control circuit transmits the data to the computer host, and if the data contains error bits, the error correcting process executed by the error correcting circuit will try to correct the error. If the number of error bits is within a correctable range, the error bits are corrected and the control circuit transmits the corrected data to the computer host. Contrarily, if the number of error bits exceeds the correctable range, the control circuit notifies the computer host that the data is lost.
Generally speaking, the flash memory in a flash memory storage device has a plurality of physical blocks, and a flash memory controller of the flash memory storage device logically groups these physical blocks into a system area, a data area, a spare area, and a replacement area. To be specific, the physical blocks in the system area are used to store important information related to the flash memory storage device, and the physical blocks in the replacement area are used to replace damaged physical blocks in the data area or the spare area. Accordingly, a host system cannot access the physical blocks in the system area and the replacement area in a general access state. The physical blocks in the data area are used to store valid data written by write commands, and the physical blocks in the spare area are used to substitute the physical blocks in the data area when the write commands are executed. To be specific, when the flash memory storage device receives a write command from the host system and is about to update (or write data into) a physical block in the data area, the flash memory storage device selects a physical block from the spare area and writes both the old valid data in the physical block to be updated in the data area and the new data into the physical block selected from the spare area. After that, the flash memory storage device logically links the physical block containing the new data to the data area, erases the physical block to be updated in the data area and links it to the spare area. The flash memory storage device provides logical blocks to the host system in order to allow the host system to successfully access the physical blocks which are alternatively used for storing data. Namely, the flash memory storage device reflects the alternation of the physical blocks by recording and updating the mapping relationship between the logical blocks and the physical blocks in the data area in a logical address-physical address mapping table. Thereby, the host system simply writes data into the logical blocks while the flash memory storage device reads data from or writes data into the corresponding physical blocks according to the logical address-physical address mapping table.
According to the operation mechanism described above, when data is copied from one physical block to another physical block, the error correcting circuit always executes the error correcting process while reading data, re-generates the error correcting code according to the corrected data while writing data, and eventually writes the corrected data and the newly generated error correcting code into the other physical block. However, if error bits that cannot be corrected are found when the error correcting process is executed, because the error correcting code is re-generated according to the error data, when subsequently the data is read by the computer host, the error correcting circuit executes the error correcting process to the error data according to the re-generated error correcting code and accordingly determines the data to be accurate. In this case, the computer host will receive the error data, and in particular, the computer host will use this error data as an accurate data.
Nothing herein should be construed as an admission of knowledge in the prior art of any portion of the present invention. Furthermore, citation or identification of any document in this application is not an admission that such document is available as prior art to the present invention, or that any reference forms a part of the common general knowledge in the art.